Athlon XP [ Paromino & Morgan ]

The following report is applicable the Barton and Thoroughbred.
However, my presumed part is contained. Please confirm for yourself.

Multiplier Signal Circuits

We think that the multiplier of Palomino is as follows.


Multiplier control circuit for the palomino

If you are using Motherboard which cannot control the Multiplier, the following circuits are added to it.
The multiplier is controllable by this circuit. It is not necessary to touch the FIDpins.


BP_FID[4:0] SYSCLK Multiplier Combinations

MultiplierClock
(FSB133)
BP-FID[4:0]Model#
5.0x 667MCC:CC -
5.5x 733MCC:C: -
6.0x 800MCC::C -
6.5x 867MCC::: -
7.0x 933MC:CCC -
7.5x1.00GC:CC: -
8.0x1.07GC:C:C -
8.5x1.13GC:C:: -
9.0x1.20GC::CC -
9.5x1.27GC::C: -
10.0x1.33GC:::C1500+
10.5x1.40GC::::1600+
11.0x1.47GCCCCC1700+
11.5x1.53GCCCC:1800+
12.0x1.60GCCC:C1900+
12.5x1.67GCCC::2000+
MultiplierClock
(FSB133)
BP-FID[4:0]Model#
13.0x1.73G:C:CC2100+
13.5x1.80G:C:C: -
14.0x1.87G:C::C -
*** - :C::: -
15.0x2.00G::CCC -
*** - ::CC: -
16.0x2.13G::C:C -
16.5x2.20G::C:: -
17.0x2.27G:::CC -
18.0x2.40G:::C: -
*** - ::::C -
*** - ::::: -
3.0x - :CCCC -
*** - :CCC: -
4.0x - :CC:C -
*** - :CC:: -

: = down (logic level of 1) , C = Up (logic level of 0)


Pin diagram of Socket A

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